Computer Science 343 - Laboratory
Introduction In CS 343 Laboratory, students will design a simple, pipelined RISC-style microprocessor, using the Hardware Description Language VHDL. The labs are structured to allow the students to gradually acquire necessary skills and build up smaller, less complex components in the initial phases of the project. These simpler components will then be combined into more complex elements which illustrate and implement more advanced concepts, as they are introduced in lecture. Schedule Requirements If you must miss lab because of illness or other good reason, I expect you to notify me ahead of time, and I will then allow you to schedule a time to make up your lab with me. That will normally have to be some time on Tuesday or Wednesday, since that is when I am on campus. Also, you must make up the lab before the next lab meeting. Grading Completing all labs is mandatory - you will receive no lab credit if you miss one or more sessions. Laboratories
Jean Herbst --
jherbst@firstclass.wellesley.edu |