|
Date |
Lecture Number |
Subject |
Reading |
In
|
Out
|
|
M 1/28 |
1 |
Introduction to Programmable Logic |
-
|
- |
-
|
|
W 1/30 |
- |
Lab 1 - Introduction to Xilinx |
- |
- |
- |
|
Th 1/31 |
2 |
Introduction to VHDL |
VHDL Tutorial Chapter 1
|
- |
HW 1
|
|
M 2/4 |
3 |
Basic VHDL Syntax |
VHDL Tutorial Chapter 2, Chapter 4: 4.1
|
- |
-
|
|
W 2/6 |
- |
Lab 2 - Basic VHDL Programming |
- |
- |
- |
|
Th 2/7 |
4 |
VHDL Control Structures |
VHDL Tutorial Chapter 3
|
HW 1
|
HW 2
|
|
M 2/11 |
5 |
VHDL Modeling Constructs |
VHDL Tutorial Chapter 5
|
-
|
-
|
|
W 2/13 |
- |
Lab 3 - VHDL Behavioral Architectures |
- |
- |
- |
|
Th 2/14 |
6 |
VHDL Subprograms and Generics |
VHDL Tutorial Chapter 7: 7.1 - 7.4, Chapter 12
|
-
|
-
|
|
M 2/18 |
-
|
NO CLASSES
|
-
|
-
|
-
|
W 2/20 |
-
|
Lab 4 - Instruction Interpreter for Mini-MIPS |
-
|
-
|
-
|
|
Th 2/21 |
7 |
VHDL Example - A Memory Model |
-
|
HW 2
|
HW 3
|
M 2/25 |
8
|
Review of the Single-cycle CPU
The Multi-cycle CPU I |
Patterson Chapter 5: 5.1 -5.5
|
-
|
-
|
|
W 2/27 |
- |
Lab 5 - Instruction Interpreter for Mini-MIPS |
- |
- |
- |
|
Th 2/28 |
9 |
The Multi-cycle CPU II |
Patterson Chapter 5: 5.5, 5.9 - 5.11
|
- |
- |
M 3/3 |
10
|
The Multi-cycle CPU III |
Patterson Chapter 5: 5.5, 5.9 - 5.11
|
-
|
Architecture and Advanced Topic Choices
|
|
W 3/5 |
- |
Lab 6 - Multi-cycle CPU |
- |
- |
- |
|
Th 3/6 |
11 |
Overview of Pipelining |
Patterson Chapter 6: 6.1
|
HW 3
|
HW 4
|
M 3/10 |
12
|
A Pipelined Data Path |
Patterson Chapter 6: 6.2 - 6.3
|
-
|
-
|
|
W 3/12 |
- |
Lab 7 - Multi-cycle CPU, Pipelined CPU |
- |
- |
- |
|
Th 3/13 |
13 |
Data Hazards and Forwarding
|
Patterson Chapter 6: 6.4 - 6.5
|
-
|
- |
M 3/17 |
14
|
Control Hazards and Exceptions |
Patterson Chapter 6: 6.6 - 6.8
|
-
|
-
|
|
W 3/19 |
- |
Lab 8 - Pipelined CPU |
- |
- |
- |
|
Th 3/20 |
15
|
Advanced Pipelining Topics |
Patterson Chapter 6: 6.9 - 6.12
|
HW 4
|
-
|
M 3/24 |
-
|
NO CLASS - SPRING BREAK
|
-
|
-
|
-
|
|
W 3/26 |
- |
NO LAB - SPRING BREAK
|
- |
- |
- |
|
Th 3/27 |
-
|
NO CLASS - SPRING BREAK
|
-
|
-
|
-
|
|
M 3/31 |
16
|
The Basics of the Memory Hierarchy and Caches |
Patterson Chapter 7: 7.1 - 7.2
|
- |
HW 5
|
|
W 4/2 |
- |
Lab 9 - Data Hazards and Forwarding |
- |
- |
- |
|
Th 4/3 |
17
|
Measuring and Improving Cache Performance and Virtual Memory |
Patterson Chapter 7: 7.3 - 7.4
|
Architecture and Advanced Topic Choices
|
-
|
|
M 4/7 |
18
|
Advanced Memory Topics |
Patterson Chapter 7: 7.5 - 7.8
|
- |
- |
|
W 4/9 |
- |
Lab 10 - Memory Implementation |
- |
- |
- |
|
Th 4/10 |
19
|
Catch up and/or review |
|
HW 5
|
-
|
|
M 4/14 |
20
|
EXAM |
|
-
|
-
|
|
W 4/16 |
- |
Lab 11 - Memory Implementation |
- |
- |
- |
|
Th 4/17 |
21
|
Student Led Discussion - Architecture |
TBA
|
-
|
-
|
|
M 4/21 |
-
|
NO CLASS
|
-
|
- |
- |
T 4/22 |
22
|
MONDAY SCHEDULE
Student Led Discussion - Architecture |
TBA
|
-
|
-
|
|
W 4/23 |
- |
Lab 12 - TBA |
- |
- |
- |
|
Th 4/24 |
23
|
Student Led Discussion - Architecture |
TBA
|
-
|
-
|
|
M 4/28 |
24
|
Student Led Discussion - Advanced Topic |
TBA
|
-
|
-
|
|
W 4/30 |
- |
NO LAB
RUHLMAN CONFERENCE |
- |
- |
- |
|
Th 5/1 |
25
|
Student Led Discussion - Advanced Topic |
TBA
|
-
|
-
|
|
M 5/5 |
26
|
Student Led Discussion - Advanced Topic |
TBA
|
- |
- |
|
W 5/7 |
- |
Lab 13 - NO LAB |
- |
- |
- |