|
Date
|
Lecture Number
|
Subject
|
Reading
|
In
|
Out
|
|
T 2/1
|
1
|
Course Introduction
|
Patterson Chapter 1, Appendix A: A.1 - A.4
|
-
|
-
|
|
W 2/2
|
-
|
Lab 0
|
-
|
-
|
|
|
F 2/4
|
2
|
Review of Digital Logic
|
Patterson Appendix B: B.1 - B.3, B.5, B.7 - B.8
|
-
|
HW 1
|
|
T 2/8
|
3
|
Introduction to VHDL
|
VHDL Tutorial Chapters 1 and 2
|
-
|
-
|
|
W 2/9
|
-
|
Lab 1
|
-
|
-
|
-
|
|
F 2/11
|
4
|
Basic VHDL Syntax
|
VHDL Tutorial Chapter 3: 3.1 - 3.3, 3.5
|
HW 1
|
HW 2
|
|
T 2/15
|
5
|
VHDL Control Structures
|
VHDL Tutorial Chapter 3: 3.4, Chapter 4: 4.1
|
-
|
-
|
|
W 2/16
|
-
|
Lab 1
|
-
|
-
|
-
|
|
F 2/18
|
6
|
VHDL Modeling Constructs
|
VHDL Tutorial Chapter 4: 4.2 - 4.3, Chapter 8
|
-
|
-
|
|
T 2/22
|
7
|
VHDL Generics
Introduction to MIPS I
|
VHDL Tutorial Chapter 8 Patterson Chapter 2: 2.1 - 2.3
|
HW 2
|
HW 3
|
|
W 2/23
|
-
|
Lab 2
|
-
|
-
|
-
|
|
F 2/25
|
8
|
Introduction to MIPS II
|
Patterson Chapter 2: 2.4 - 2.9
|
-
|
-
|
|
T 3/1
|
9
|
MIPS Arithmetic I
|
Patterson Chapter 3: 3.1 - 3.6
|
-
|
-
|
|
W 3/2
|
-
|
Lab 2
|
-
|
-
|
-
|
|
F 3/4
|
10
|
MIPS Arithmetic II Assessing and Understanding Performance
I
|
Patterson Chapter 3: 3.6, 3.9 Chapter 4: 4.1
|
-
|
-
|
|
T 3/8
|
11
|
Assessing and Understanding Performance II
|
Patterson Chapter 4: 4.1 - 4.2
|
HW 3
|
HW 4
|
|
W 3/9
|
-
|
Lab 3
|
-
|
-
|
-
|
|
F 3/11
|
12
|
Assessing and Understanding Performance III
|
Patterson Chapter 4: 4.3 - 4.6
|
-
|
-
|
|
T 3/15
|
13
|
Assessing and Understanding Performance Experiment
The
Processor: Data Path and Control I |
Patterson Chapter 5: 5.1 - 5.2
|
HW 4
|
-
|
|
W 3/16
|
-
|
Lab 3
|
-
|
-
|
-
|
|
F 3/18
|
14
|
MIDTERM EXAM
|
-
|
-
|
Architecture Choice
|
|
T 3/22
|
-
|
NO CLASS
SPRING BREAK |
-
|
-
|
-
|
|
W 3/23
|
-
|
NO LAB
SPRING BREAK |
-
|
-
|
-
|
|
F 3/25
|
-
|
NO CLASS
SPRING BREAK |
-
|
-
|
-
|
|
T 3/29
|
15
|
The Processor: Data Path and Control II
|
Patterson Chapter 5: 5.3 - 5.4
|
-
|
-
|
|
W 3/30
|
-
|
Lab 4
|
-
|
-
|
-
|
|
F 4/1
|
16
|
The Processor Data Path and Control III
|
Patterson Chapter 5: 5.4 - 5.5
|
Architecture Choice
|
HW 5
|
|
T 4/5
|
17
|
The Processor Data Path and Control IV
|
Patterson Chapter 5: 5.5
, 5.9 - 5.11
|
-
|
-
|
|
W 4/6
|
-
|
Lab 4
|
-
|
-
|
-
|
|
F 4/8
|
18
|
Enhancing Performance with Pipelining I
|
Patterson Chapter 6: 6.1
|
HW 5
|
HW 6
|
|
T 4/12
|
19
|
Enhancing Performance with Pipelining II
|
Patterson Chapter 6: 6.9 - 6.12
|
-
|
-
|
|
W 4/13
|
-
|
Lab 5
|
-
|
-
|
-
|
|
F 4/15
|
20
|
The Memory Hierarchy I |
Patterson Chapter 7: 7.1 - 7.2
|
HW 6
|
HW 7
|
|
T 4/19
|
-
|
NO CLASS
MONDAY SCHEDULE |
-
|
-
|
-
|
|
W 4/20
|
-
|
Lab 5
|
-
|
-
|
-
|
|
F 4/22
|
21
|
The Memory Hierarchy II
|
Patterson Chapter 7: 7.3 - 7.5
|
-
|
-
|
|
T 4/26
|
22
|
Karyn Benson
|
TBA
|
HW 7
|
-
|
|
W 4/27
|
-
|
Lab 6
|
-
|
-
|
-
|
|
F 4/29
|
23
|
Christine Simpson
|
TBA
|
-
|
-
|
|
T 5/3
|
24
|
Kelsey Peterson
|
TBA
|
-
|
-
|
|
W 5/4
|
-
|
NO LAB
RUHLMAN CONFERENCE |
-
|
-
|
-
|
|
F 5/6
|
25
|
Victoria Derau
|
TBA
|
-
|
-
|
|
T 5/10
|
26
|
Tori Woodhouse
|
TBA
|
-
|
-
|
|
W 5/11
|
-
|
Lab 6
|
-
|
-
|
-
|