CS 240 Lab 5

Learning Goals & Reflection

CS 240 Lab 5

• Lab slides
• Lab notebook

Learning Goals

Core Goals

Students can:

1. Explain the operation of random access memory: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Explain what “random” means in the term “random access memory.”
   2. Explain the difference between address and data inputs for a RAM.
   3. Explain how the “write enable” input for a RAM works.
   4. Explain how to calculate the number of address inputs needed for a RAM that holds a certain number of words.
   5. Explain how to calculate the total size of a ram in bits/bytes based on the word size, the number of address bits, and whether it is byte-addressable or word-addressable.
2. Explain how a program counter works: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Explain the purpose of the PC within a Central Processing Unit.
   2. Identify which RAM input the PC feeds into.
   3. Explain the feedback loop that advances the program counter each clock cycle.
3. Explain the relationship between data, voltage patterns in computer chips, and programs: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Explain how voltage patterns on wires in RAM can represent numbers.
   2. Explain how numbers can represent computer instructions.
   3. Explain how using a program counter mechanism, sequences of voltage patterns in RAM can act as a program.
4. Explain the details of the HW ISA: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Translate between machine instructions and assembly syntax for the HW ISA using the HW ISA Instructions slide.
   2. Identify the limitations of the HW ISA imposed by the instruction encoding in terms of: 1) the number of registers in the register file, 2) the possible offsets for BEQ and JMP instructions.
   3. Identify the limitations of the HW ISA imposed by the register size in terms of: 1) The word size for RAM, 2) the maximum size of the RAM address space.
   4. Referring to the HW ISA Instructions slide, simulate the execution of instructions in the HW ISA and fill in PC values, register values, and data memory contents based on the contents of instruction memory and some initial state.
5. Explain the details of the HW Arch microarchitecture: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Explain the relationship between an Instruction Set Architecture and a Microarchitecture.
   2. Explain the purpose of the control unit in the HW Arch.
   3. Explain how the control unit fulfils its purpose by sending select signals to strategically-placed multiplexers throughout the CPU.
   4. Write a full truth table for the control unit.
   5. Translate machine instructions into control unit outputs and register file inputs, and vice versa.
   6. Explain how the BEQ instruction is implemented: which data path does it feed into, and where does it get the value which is added to the PC when a BEQ instruction is processed?

Stretch goals

1. Explain the operation of random access memory: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Explain the purpose of a decoder within a RAM circuit.
   2. Explain the purpose of tri-state buffers on the output side of a RAM circuit.
2. Explain the relationship between data, voltage patterns in computer chips, and programs: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Explain how numbers can represent text.
   2. Explain what is likely to happen if non-program data is loaded as a program.
   3. Explain what is likely to happen if program data is loaded as text.
3. Explain the details of the HW ISA and the HW Arch microarchitecture: (Your mastery: 0 - No knowledge 1 - Learning 2 - Mastering 3 - Mastered )
   1. Explain why instructions have at most two source registers and one destination register.
   2. Explain why there are no instructions which both read from and write to memory.
   3. Design simple programs involving integer inputs and outputs in HW ISA assembly code.
   4. Explain how the JMP instruction could be implemented in the HW Arch microarhcitecture.

Reflection